A data switch has the purpose of receiving digital data introduced by transmission lines, sorting such data, and then regrouping it in order to re-send it over suitable transmission lines.
Such lines are often associated by pairs, comprising a receive line and a send line providing a link with a similar remote station. These pairs of lines are connected in parallel to a bus referred to as the transmission bus, carrying line coupling modules which manage access of the transmission lines to the transmission bus. A transmission bus coupling module (CBT) provides transfer of the data received towards the processing means of the switch, and the transfer of the data that has been processed and regrouped in the switch, towards the sending lines connected to the transmission bus.
The transmission bus coupling module (CBT) interrogates the lines by polling cycles in send mode and then in receive mode. Systematically, if a line polled in receive mode is in possession of a received character, (a byte of data received from the line), the transmission bus coupling module performs, via the transmission bus, a data transfer cycle by means of which it recovers the character and stores it in its data memory in a buffer register dedicated to the line that was interrogated in receive mode (receive line memory). If a line polled in send mode calls for a character to be sent (data byte to be sent over the line), the transmission bus coupling module executes a data transfer cycle by means of which it takes the character to be sent from its data memory and transmits it to the line.
This invention more particularly concerns the receive mode line memory of the transmission bus coupling module.
These receive mode line memories are accessed by read and write devices which operate independently. Operation of the write device depends on occurrence of the enabling signal for access from the receive line to the transmission bus, and of the start of the data carried by the receive line. Operation of the read device is put under the control of access enablement to the processing means that are internal to the switch. When the receive mode line buffer memory has a limited capacity, reception overload can consequently occur, in other words the speed of writing into the memory is greater, in a lasting manner, than the speed of reading the preceding data. If the buffer memory is a rotating memory (of the FIFO type), this reception overload can manifest itself by the least recent data being overwritten with a consequent definitive loss of such data.
Systems are known which aim at managing reception overloads.
These known systems operate using a principal of monitoring the occupancy rate of the receive line memory, with marking of the passage beyond successive occupancy thresholds giving rise to the generation of interrupt signals to a supervisory microprocessor in charge of managing the transmission bus coupling module. Under command of such interrupt signals, this supervisory microprocessor commands partial or total readout of the buffer memory by initializing the read means through direct memory access (DMA). With a known system of this type, the risk of overwriting is kept in check. If the system operates perfectly, elimination of conditions for overwriting is achieved. Still, it is also possible to tolerate some overwriting of data. In this case, in a known manner, the system is provided with means for detecting character loss generally at the level of the means for processing the received data, which means command a repetition of the transmission of the lost data.
Whatever the operating conditions are, (overwriting eliminated or tolerated), this known mechanism for supervision using the generation of interrupt signals suffers from the disadvantage of tying up or monopolizing the microprocessor. The program run by the supervisory microprocessor must in effect include a supervisory task for the occupancy level of the receive line memory, which needs to be run for each line in receive mode, and this has the effect of burdening the administration microprocessor's overall power.
The framework of the invention is that of a transmission arrangement in which data overwriting is tolerated, and has notably the aim of providing a system for detecting overwriting of data at buffer memory level without the microprocessor responsible for administering the transmission bus coupling module requiring to manage a supervisory task for the whole set of buffer memories in the reception lines.